Unified systolic array architecture for finite field multiplication and inversion. (July 2017)

• Record Type: Journal Article
• Authors: Ibrahim, Atef; Alsomani, Turki; Gebali, Fayez
• Is Part Of: Computers & electrical engineering. Volume 61(2017)
• Page Start: 104
• Page End: 115
• Publication Date: 2017-07
• Subjects: Finite field inversion -- Cryptosystems -- Systolic arrays -- Hardware security -- Resource-constrained applications -- ASIC; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2017.06.014
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: Propose a regular technique for exploring the unified hardware structure. Develop a novel unified systolic array structure for the multiplication and inversion algorithms over GF (2 m ). Provide ASIC and FPGA implementations for the proposed and the previously published designs. Graphical abstract: Unified Systolic Array Structure for Multiplication and Inversion Over GF(2 m ). Abstract: This paper proposes a new unified systolic array architecture to perform multiplication and inversion operations in GF (2 m ) based on the bit serial multiplication algorithm and the previously modified extended Euclidean algorithm. This architecture is explored by applying a regular technique to the multiplication and inversion algorithms. It has lower area and power complexities as well as it achieves a moderate speed. Also, it has a simple structure with processing elements have local communication with each other. The implementation results of the proposed design and the comparable published designs show that the proposed design saves more area (ranging from 18.8% to 23.0%) and saves more energy (ranging from 18.2% to 47.0%) over the compared efficient designs. This makes it more suitable for applications that impose more constraints on area and power consumption.