(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2n+1) unified adder/subtractor with full zero handling. (July 2017) - Jaberipur, Ghassem; Belghadr, Armin
Abstract: Performance of modulo-(2 n  + 1) arithmetic is enhanced via D1 encoding versus normal ( n  + 1)-bit encoding of residues in   [0,   2 n ]. Faster modulo-(2 n  + 1) operations promote the latency balance with the commonly companion modulus (2 n  − 1) and 2 n in residue number system arithmetic. However, the cases of zero inputs/output of D1 arithmetic circuits entail especial handling, with some overhead. Despite many studies over modulo-(2 n  + 1) D1 adders, where the least achieved latency is (3+ 2⌈log  n ⌉)Δ G, there has been few works on the D1 subtraction. However, the lowest reported performance for the latter is (7+ 2⌈log  n ⌉)Δ G . In this paper, we revisit the fastest previous (D1 adder, propose an as fast D1 subtractor, and a (5+ 2⌈log  n ⌉)Δ G unified D1 adder/subtractor, with minimal unification overhead (i.e., one XOR/bit), all with full zero handling. Compared to the best of previous relevant works, we demonstrate 18–34% less delay and 5–18% less energy for the ensemble three modulus of the set {2 n  − 1, 2 n,  2 n  + 1}.