Chip implementation of supervised neural network using single-transistor synapses. (August 2017)

• Record Type: Journal Article
• Authors: Jeng, E.S.; Chou, S.W.; Chen, H.X.; Chiang, Y.L.
• Is Part Of: Microelectronics journal. Volume 66(2017)
• Page Start: 76
• Page End: 83
• Publication Date: 2017-08
• Subjects: Single transistor synapse -- Neural network chip -- Pattern recognition; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.06.001
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this work, the newly developed neural chip applied in analog inputs for on-chip training and recognition is presented. We have designed the neural chip using single-transistor synapses which are capable of storing analog weights. The neural chip includes the interface circuit, power switches, analog synaptic array (7 × 4 synapses), and transresistance amplifiers (TR_AMPs) for on-chip training and recognition. Voice signals were acquired using analog signal processing and conditioning circuits for use in verifying the chip's pattern recognition functionality. The experimental results reveal that the synaptic weights of the neural network have adapted with training and have gradually converged to the targets afterwards. Upon system convergence, the recognition rates of the targeted speaker and the three others were evaluated. By using very small amount of synapses, as few as 28 synapses, the system's successful recognition rate for the targeted speaker is 93.5% for 200 tests; whereas, the rate for the other speakers is approximately 6.3% for 600 tests.