A fault-analysis oriented re-design and cost-effectiveness evaluation methodology for error tolerant applications. (August 2017) - Hsieh, Tong-Yu; Li, Kuan-Hsien; Chung, Chen-Chia
Abstract: For error-tolerant applications such as multimedia circuits, the circuits can be re-designed by removing the hardware that contains faults inducing only imperceptible errors for human beings. As a result, the area, critical path delay and power consumption of the circuits can become much lower. The chip yield can thus also be improved. However, this method also sacrifices the inherent error-tolerability of the circuits when they suffer from noises such as soft errors in the field. For IoT (Internet of Things) applications, this issue is critical for cost-effectively extending their lifetime, and should be considered, which however is not addressed in the literature. In this paper we will show that performing fault analysis can make the evaluation of the incurred cost in error tolerability easy to be carried out. A fault-analysis oriented methodology is presented in this work to help users develop and evaluate re-design methods for their applications. In the proposed methodology, selection of fault models and implementation of fault injection and evaluation processes is addressed. According to the evaluation results, non-critical hardware parts are identified and removed. Furthermore, yield and error-tolerability evaluation models are presented. We also apply the proposed methodology to the JPEG2000 image encoding process as a case study. The quantitative analysis results conducted in this case study illustrate the importance of evaluating the adverse impact on error-tolerability.