On-chip training of memristor crossbar based multi-layer neural networks. (August 2017)

• Record Type: Journal Article
• Authors: Hasan, Raqibul; Taha, Tarek M.; Yakopcic, Chris
• Is Part Of: Microelectronics journal. Volume 66(2017)
• Page Start: 31
• Page End: 40
• Publication Date: 2017-08
• Subjects: Neural networks -- Memristor crossbars -- Training -- On-chip training; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.05.005
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Memristor crossbar arrays carry out multiply-add operations in parallel in the analog domain, and so can enable neuromorphic systems with high throughput at low energy and area consumption. On-chip training of these systems have the significant advantage of being able to get around device variability and faults. This paper presents on-chip training circuits for multi-layer neural networks implemented using a single crossbar per layer and two memristors per synapse. Using two memristors per synapse provides double the synaptic weight precision when compared to a design that uses only one memristor per synapse. Proposed on-chip training system utilizes the back propagation (BP) algorithm for synaptic weight update. Due to the use of two memristors per synapse, we utilize a novel technique for error back propagation. We evaluated the training of the system with some nonlinearly separable datasets through detailed SPICE simulations which take crossbar wire resistance and sneak-paths into consideration. Our results show that in the proposed design, the crossbars consume about 9× less power than single memristor per synapse design.