Optimization of printed circuit board interconnectivity testing for parallel devices. Issue 10 (3rd October 2017) - Mo, Jeonghoon
ABSTRACT: In this article, the problems of test sequence generation and scheduling optimization for a tester with parallel devices are considered in order to reduce inspection times. Two optimization problems are formulated for test sequence generation and the scheduling of parallel devices, and then algorithms to address these problems are proposed. The proposed algorithms were tested via simulation and experiments. The test results show two to four times improvement over existing methods.