Exploring one‐sided communication and synchronization on a non‐cache‐coherent many‐core architecture. (29th March 2017)

• Record Type: Journal Article
• Authors: Christgau, Steffen; Schnor, Bettina
• Other Names: Lengauer Christian guestEditor.; Bougé Luc guestEditor.; Trystram Denis guestEditor.; Balaji Pavan guestEditor.; Leung Kai‐Cheung guestEditor.
• Is Part Of: Concurrency and computation. Volume 29:Number 15(2017)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2017-03-29
• Subjects: MPI -- one‐sided communication -- programming models and systems for many‐cores -- synchronization -- software‐managed cache coherence; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.4113
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: The ongoing many‐core design aims at core counts where cache coherence becomes a serious challenge. Therefore, this paper discusses how one‐sided communication and the required process synchronization can be realized on a non‐cache‐coherent many‐core CPU. The Intel Single‐chip Cloud Computer serves as an exemplary hardware architecture. The presented approach is based on software‐managed cache coherence for MPI one‐sided communication. The prototype implementation delivers a PUT performance of up to 5 times faster than the default message‐based approach and reveals a reduction of the communication costs for the NAS Parallel Benchmarks 3‐D fast Fourier Transform by a factor of 5. Further, the paper derives conclusions for future non‐cache‐coherent architectures.