Manipulating III–V Nanowire Transistor Performance via Surface Decoration of Metal‐Oxide Nanoparticles. Issue 12 (8th May 2017)

• Record Type: Journal Article
• Authors: Wang, Fengyun; Yip, SenPo; Dong, Guofa; Xiu, Fei; Song, Longfei; Yang, Zaixing; Li, Dapan; Hung, Tak Fu; Han, Ning; Ho, Johnny C.
• Is Part Of: Advanced materials interfaces. Volume 4:Issue 12(2017)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2017-05-08
• Subjects: enhancement modes -- III–V nanowires -- metal‐oxide nanoparticles -- surface decoration -- threshold voltage; Materials science -- Periodicals; 620.11
• DOI: 10.1002/admi.201700260
• Languages: English
• ISSNs: 2196-7350

Abstract

Abstract : Recently, III–V semiconductor nanowires (NWs) are widely investigated as field‐effect transistors (FETs) for high‐performance electronics, optoelectronic, and others; nevertheless, effective control in their device performances, especially the threshold voltage is still not well attained, which can potentially limit their practical uses for technological applications. This study reports a simple but highly reliable metal‐oxide nanoparticle (NP) surface decoration approach onto the device channel in order to manipulate electrical characteristics of III–V NWFETs, such as the threshold voltage and transistor operation, through the manipulation of free electrons in the NW channel (i.e., InAs, InP, and In0.7 Ga0.3 As) via depositing various metal‐oxide NPs with different work functions. Without any passivation layer, this decoration approach can yield the stable NW device characteristics in ambient. Notably, the versatility of our decoration scheme has also been illustrated through the realization of high‐performance enhancement‐mode InAs NW‐paralleled‐arrayed devices as well as the configuration of highly efficient InAs NW NMOS inverters, comprising of both depletion and enhancement mode devices. All these results further elucidate the technological potential of this decoration approach for future high‐performance, low‐power nanoelectronic device fabrication, and circuit integration. Abstract : A metal‐oxide decoration scheme is utilized to modulate electronic transport properties (e.g., threshold voltage) of III–V nanowire (NW) field‐effect transistors through adjusting the free carriers in NW channels via decorating different metal‐oxide nanoparticles with different work functions. InAs NW inverters based on intrinsic D‐mode and metal‐oxide nanoparticles decorated E‐mode InAs NW‐paralleled‐arrayed transistors further demonstrate the versatility of this technique for future nanoelectronic device fabrication and circuit integration.