Nanowire Transistors: Manipulating III–V Nanowire Transistor Performance via Surface Decoration of Metal‐Oxide Nanoparticles (Adv. Mater. Interfaces 12/2017). Issue 12 (June 2017)

• Record Type: Journal Article
• Authors: Wang, Fengyun; Yip, SenPo; Dong, Guofa; Xiu, Fei; Song, Longfei; Yang, Zaixing; Li, Dapan; Hung, Tak Fu; Han, Ning; Ho, Johnny C.
• Is Part Of: Advanced materials interfaces. Volume 4:Issue 12(2017)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2017-06
• Subjects: enhancement modes -- III–V nanowires -- metal‐oxide nanoparticles -- surface decoration -- threshold voltage; Materials science -- Periodicals; 620.11
• DOI: 10.1002/admi.201770060
• Languages: English
• ISSNs: 2196-7350

Abstract

Abstract : Ning Han, Johnny C. Ho, and co‐workers develop a metal‐oxide decoration scheme to modulate threshold voltage of III‐V nanowire FETs through adjusting free carriers in the nanowire channel via decorating various metal‐oxide nanoparticles with different work functions in article number1700260 . Low‐power InAs nanowire NMOS inverters, based on pristine depletion‐mode and metal‐oxide nanoparticles decorated enhancement‐mode InAs NW‐parallel‐arrayed transistors, can demonstrate the versatility of this technique for future high‐performance nanoelectronics.