A constrained optimization approach for accurate and area efficient bandgap reference design. (July 2017)

• Record Type: Journal Article
• Authors: de Andrade, Allan B.; Petraglia, Antonio; Soares, Carlos F.T.
• Is Part Of: Microelectronics journal. Volume 65(2017)
• Page Start: 72
• Page End: 77
• Publication Date: 2017-07
• Subjects: Bandgap reference -- CMOS analog integrated circuit -- Optimization -- Temperature coefficient; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.05.012
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, a constrained optimization approach for the design of bandgap reference (BGR) circuits that meet a given voltage inaccuracy specification while minimizing area is presented. Device matching properties and error propagation analysis are carried out such that the desired performance can be achieved by the optimization algorithm. The BGR occupies 0.097 mm 2 in a 0.35 μ m CMOS process. Experimental results verified the effectiveness of the optimization algorithm by producing a voltage reference of 1.220 V, with a relative inaccuracy ( 3 σ / μ ) of 0.65 % at 27 ° C and TC = 13.7 ppm / ° C in the range of − 10 ° C to 125 ° C, for all 40 fabricated samples, without trimming. Also shown in the paper and verified experimentally, a 3-fold reduction in inaccuracy, to 0.20% at 27 ° C, can further be obtained, if needed, by a simple one-temperature four-bit trimming.