Numerical modeling and implementation in circuit simulator of SOI four-gate transistor (G4FET) using multidimensional Lagrange and Bernstein polynomial. (July 2017)

• Record Type: Journal Article
• Authors: Hasan, Md Sakib; Rahman, Touhidur; Islam, Syed K.; Blalock, Benjamin B.
• Is Part Of: Microelectronics journal. Volume 65(2017)
• Page Start: 84
• Page End: 93
• Publication Date: 2017-07
• Subjects: Silicon-on-insulator (SOI) -- Multiple-gate transistor -- G4FET -- Lagrange polynomial -- Bernstein polynomial; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.05.011
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents two efficient numerical models developed for simulating circuits containing silicon-on-insulator four-gate transistors (G 4 FET). First the model is developed using one set of available data and then it is validated using another set of test data. These models provide a single multivariate polynomial expression that is valid across different biasing regimes as long as it falls within the range of data set used to develop the model. Lagrange form of interpolating polynomial and Bernstein Form of approximating polynomial are used to generate these models. Both forms have the advantage of being computed from a limited number of data points. Since these polynomial models and their derivatives are continuous, they are suitable for implementation in circuit simulator. The models have been developed and validated for both n -channel and p -channel G 4 FETs using both TCAD and experimental data and are successfully implemented in SPICE simulator for simulating circuits containing G 4 FETs.