Randomly prioritized buffer-less routing architecture for 3D Network on Chip. (April 2017)

• Record Type: Journal Article
• Authors: Karthikeyan, A.; Senthil Kumar, P.
• Is Part Of: Computers & electrical engineering. Volume 59(2017)
• Page Start: 39
• Page End: 50
• Publication Date: 2017-04
• Subjects: SoC, Noc -- 3D-Noc -- Scheduling algorithm -- Round Robin algorithm -- Lottery algorithm etc; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2017.03.006
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Recently, 3D NoC has become more important than 2D NoC due its new geometrical arrangement and also reduces the wire length from global interconnect to local interconnect. One of the main components to implement 3D NoC is the router. The components of the router are crossbar, FIFO, and arbiter. The scheduling algorithm is the main part of the arbiter which schedules and delivers all packets to the destination nodes without any loss of packets. Packets that have the highest priority are served first, the remaning highest priority packets ares queued in the priority register and non-priority packets are served after all priority packets are served. Round Robin routing algorithm is commonly used as the scheduling algorithm in most of the routers. This paper proposes a novel 3D lottery routing algorithm which is based on arbitral mechanism like randomly prioritized buffer. Communication among the IPs in NoC can be customized by users through the lottery router. The lottery routing algorithm distinguishes the different priorities of the input port and makes sure that it responses to the higher priority port. The efficient hardware implementation of 3D NoC is proposed using Xilinx Spartan 3E FPGA, the result shows that the proposed architecture consumes 1644 slices out of 4656 slices and operates at the maximum frequency of about 103.602 MHz. The 3D NoC is modeled and implemented with a Cadence Electronic Design Automation tool and the results show that the power consumption of 3D NoC is reduced by 9% compared to a single layer.