Implementation of a noise-coexistence threshold logic architecture on a GaAs-based nanowire FET network. Issue 3 (4th May 2017)

• Record Type: Journal Article
• Authors: Kuroda, Ryota; Kasai, Seiya
• Is Part Of: International journal of parallel, emergent and distributed systems. Volume 32:Issue 3(2017)
• Page Start: 287
• Page End: 294
• Publication Date: 2017-05-04
• Subjects: Word -- semiconductor nanowire network -- threshold logic -- hysteresis -- noise; Parallel computers -- Periodicals; Electronic data processing -- Distributed processing -- Periodicals; Computer algorithms -- Periodicals; 004.35
• DOI: 10.1080/17445760.2016.1201673
• Languages: English
• ISSNs: 1744-5760

Abstract

Abstract: Toward reconfigurable and noise-coexistence information processing system utilizing nanostructures, we study a threshold logic circuit and a double threshold function using a GaAs-based nanowire field-effect transistor (FET) network. A noise coexistence capability is based on a noise-assisted state transition in a threshold function in a threshold logic element. We fabricate a circuit reconfigurable between NAND and NOR functions. A hysteresis transfer characteristic with double threshold is realized in the GaAs nanowire by using a silicon nitride (SiN) as the gate insulator. We introduce a unique inverter design using the SiN-gate FET as a load to achieve the transfer characteristic with clockwise hysteresis, similar to a Schmitt trigger. Abstract : Implementation of a two-variable threshold logic with double threshold function using GaAs-based nanowire FETs.