Boundary element quadrature schemes for multi- and many-core architectures. (1st July 2017)

• Record Type: Journal Article
• Authors: Zapletal, Jan; Merta, Michal; Malý, Lukáš
• Is Part Of: Computers & mathematics with applications. Volume 74:issue 1(2017)
• Page Start: 157
• Page End: 173
• Publication Date: 2017-07-01
• Subjects: Boundary element method -- Quadrature -- SIMD -- Vectorization -- Intel Xeon Phi -- Many-core architecture; Electronic data processing -- Periodicals; Mathematics -- Data processing -- Periodicals; 510.28541
• DOI: 10.1016/j.camwa.2017.01.018
• Languages: English
• ISSNs: 0898-1221

Abstract

Abstract: In the paper we study the performance of the regularized boundary element quadrature routines implemented in the BEM4I library developed by the authors. Apart from the results obtained on the classical multi-core architecture represented by the Intel Xeon processors we concentrate on the portability of the code to the many-core family Intel Xeon Phi. Contrary to the GP-GPU programming accelerating many scientific codes, the standard x86 architecture of the Xeon Phi processors allows to reuse the already existing multi-core implementation. Although in many cases a simple recompilation would lead to an inefficient utilization of the Xeon Phi, the effort invested in the optimization usually leads to a better performance on the multi-core Xeon processors as well. This makes the Xeon Phi an interesting platform for scientists developing a software library aimed at both modern portable PCs and high performance computing environments. Here we focus at the manually vectorized assembly of the local element contributions and the parallel assembly of the global matrices on shared memory systems. Due to the quadratic complexity of the standard assembly we also present an assembly sparsified by the adaptive cross approximation based on the same acceleration techniques. The numerical results performed on the Xeon multi-core processor and two generations of the Xeon Phi many-core platform validate the proposed implementation and highlight the importance of vectorization necessary to exploit the features of modern hardware.