Energy Efficient BEC Modified Carry Select Adder based PTMAC Architecture for Biomedical Processors. Issue 2 (3rd April 2017) - John Alex, E.; Vijayaraj, M.
Abstract: Power dissipation is considered as the critical objective in the design of integrated circuits. Concern has increased in the design of adders, which form the basic computational block of any circuit. Research work has been carried out towards the efficient design and performance analysis of Carry Select Adder. Carry Select Adder (CSLA) is used in many data processors to increase the speed of mathematical calculation. The main aim of this paper is to reduce the power by using Binary to Excess-1 Converter, which uses an uncomplicated and proficient gate-level adaptation to reduce the power and area of the Carry Select Adder to a tolerant level. Based on the analysis, the proposed design proves to be better than the Conventional CSLA, BEC Modified Carry Select Adder and the Regular Square Root CSLA. Moreover, the Programmable Truncated Multiplier and Accumulator Circuit architecture designed using the BEC modified CSLA can be used for low power biomedical instrumentation with a need for reticent digital signal processing like ECG fall detection, EEG filtering and others. The BEC modified CSLA has been proven efficient through its implementation in a DSP architecture with the combined benefit of fault tolerant.