Performance Improvement of Hardware/Software Architecture for Real-Time Bio Application Using MPSoC. Issue 2 (3rd April 2017)

• Record Type: Journal Article
• Authors: Arun Prasath, Raveendran; Ganesh Kumar, Parasuraman; Sakthivel, Erulappan
• Is Part Of: Intelligent automation & soft computing. Volume 23:Issue 2(2017)
• Page Start: 351
• Page End: 357
• Publication Date: 2017-04-03
• Subjects: Network-on-Chip -- Multiprocessor system-on-chip -- ECG -- Real-time analysis -- Design space exploration -- Pan tompkins algorithm -- Energy and computational time; Artificial intelligence -- Periodicals; Intelligent control systems -- Periodicals; 003.5
• DOI: 10.1080/10798587.2016.1231476
• Languages: English
• ISSNs: 1079-8587

Abstract

Abstract: In biomedical applications, the awareness in chip architectures with high performance has extended a lot of attention in market and research. A remarkable problematic situation for biomedical engineers is to monitor and analyze heart diseases, which is considered as the main reason or Electrocardiography (ECG), which plays vital role in heart medicines. Since examination of ECG meets computational tasks particularly in real time, in order to analyze the 12 lead signals in parallel with increase in sampling frequencies. Additional contest is the examination of large amounts of data to develop the times of recordings. Currently, doctors use 12-lead ECG paper information for monitoring of the eyeball, which could extremely harm analysis accuracy. In conventional work, the researchers introduced the multi-processor system-on-chip architectures to focus on the parallelization of the ECG evaluation kernel. Similar to that of conventional work in this work Hardware-Software (HW/SW) Multi-Processor System-on-Chip (MPSoC) is introduced in this proposed work. The conventional architecture is complex, which results in the performance degradation. The major focus of this method initiates its design methodology from the specifications of 12-lead ECG application to the ultimate HW/SW architecture. In this proposed work the computational complexity is very much reduced, which results the performance improvement is achieved.