Evaluation of the Interface Accuracy for Power Hardware-in-the-Loop Experiments. Issue 7 (21st April 2017)

• Record Type: Journal Article
• Authors: Paran, Sanaz; Vu, Tuyen V.; Diaz Franco, Fernand; Edrington, Chris S.
• Is Part Of: Electric power components and systems. Volume 45:Issue 7(2017)
• Page Start: 763
• Page End: 773
• Publication Date: 2017-04-21
• Subjects: converters -- power hardware-in-the-loop -- power conversion -- power systems -- interface algorithm -- inverters -- reactive power control -- real-time digital signal processing -- voltage control; Electric machinery -- Periodicals; 621.3104205
• DOI: 10.1080/15325008.2017.1294634
• Languages: English
• ISSNs: 1532-5008

Abstract

Abstract: Selecting an accurate interface algorithm is a primary goal in order to have a successful operation of power hardware-in-the-loop. The purpose of this paper is to utilize the modified damping impedance method for testing the accuracy of the interface algorithm in power hardware-in-the-loop applications in comparison to the traditional damping impedance method and ideal transformer model interfaces. The hardware-in-the-loop test-bed (a power-electronic-based system) is utilized to experimentally analyze and validate the expected advantages of the modified damping impedance method. In addition, to evaluate the power hardware-in-the-loop accuracy, a transfer function perturbation-based approach is considered to validate the results of experimentation analytically and quantitatively.