Power analysis for asynchronous network‐on‐chip. (18th October 2013)

• Record Type: Journal Article
• Authors: Abd El Ghany, Mohamed A.; Reehal, Gursharan; Ismail, Mohammed
• Is Part Of: IEEJ transactions on electrical and electronic engineering. Volume 8(2013)Supplement 1
• Page Start: S72
• Page End: S80
• Publication Date: 2013-10-18
• Subjects: NoC -- GALS -- low power -- power analysis; Electrical engineering -- Periodicals; Electronics -- Periodicals; 621.3
• DOI: 10.1002/tee.21921
• Languages: English
• ISSNs: 1931-4973

Abstract

Abstract: An asynchronous architecture is proposed to achieve a low‐power network‐on‐chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.