Performance Comparison of 64-bit Carry Look-Ahead Adders Using 32nm CMOS Technology. (2017)

• Record Type: Journal Article
• Authors: Subash, T.D.; Ajaiyan, ; Subha, T.D.
• Is Part Of: Materials today. Volume 4:Number 2(2017)Part B
• Page Start: 4153
• Page End: 4168
• Publication Date: 2017
• Subjects: Conventional domino MCC (Manchester carry chain) -- CLA (Carry look-ahead adders) -- Multi-output domino logic; Materials science -- Congresses -- Periodicals; 620.1
• DOI: 10.1016/j.matpr.2017.02.118
• Languages: English
• ISSNs: 2214-7853

Abstract

Abstract: In this paper, MCC carry chain with 8-bit carry chain proposed by Costas Efstathiou and the adder circuits were designed using 32nm CMOS technology with a supply voltage of 0.9v and the effect of temperature on the circuit performance is also analyzed in this work. For 4-bit, the input required are a 0 to a 3 and b 0 to b 3 along with initial carry cin with the sum output signals as s 0 to s 3 and the carry outputs are c 0 to c 3 . The new high speed MCC requires inputs a 0 to a 7, b 0 to b 7, cin, clock and the corresponding outputs are c 0 to c 7 and are implemented by using HSPICE.