Alternate characterization technique for static random‐access memory static noise margin determination. (27th July 2012)

• Record Type: Journal Article
• Authors: Merino, Jose Luis; Bota, Sebastia Antoni; Picos, Rodrigo; Segura, Jaume
• Is Part Of: International journal of circuit theory and applications. Volume 41:Number 10(2013:Oct.)
• Page Start: 1085
• Page End: 1096
• Publication Date: 2012-07-27
• Subjects: CMOS circuitry -- SRAM memory -- static noise margin -- predictive models; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.1832
• Languages: English
• ISSNs: 0098-9886

Abstract

ABSTRACT: The cell static noise margin (SNM) is widely used as a stability criterion for static random‐access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable. In this work, we present a methodology that provides an indirect measurement of the SNM on a per‐cell basis for six‐transistor SRAMs. It is based on combining an Adaptive Neuro‐Fuzzy Inference System (ANFIS) with circuit‐level cell experimentally measurable parameters as input variables to the tool. We show that it is possible to obtain the SNM for individual memory cells using the same experimental setup and data than that required for shmoo plot measurements. Results confirm that the SNM can be experimentally estimated with a relative error compared with electrical simulations that is below 0.5%. Copyright © 2012 John Wiley & Sons, Ltd. Abstract : The technique presented in this paper provides indirect measurements of static random‐access memories (SRAMs) cell‐level static noise margin (SNM). This method simplifies the traditional techniques used to characterize SRAM memories stability while providing accurate information. A prediction tool that combines experimental results and a fuzzy inference system is developed. The method requires the same experimental setup typically used to get shmoo plots. The relative error between SNM prediction and electrical simulation is below 0.5% for a 65‐nm technology.