A new method on designing and simulating CNTFET_based ternary gates and arithmetic circuits. (May 2017)

• Record Type: Journal Article
• Authors: Samadi, Hadi; Shahhoseini, Ali; Aghaei-liavali, Faramarz
• Is Part Of: Microelectronics journal. Volume 63(2017)
• Page Start: 41
• Page End: 48
• Publication Date: 2017-05
• Subjects: CNTFET -- MVL -- Ternary -- Gates and arithmetic circuits; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.02.018
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a new design of three-valued logic gates on the basis of carbon nanotube transistors. Next, the proposed circuit is compared with the existing models of circuits. The simulation results, using HSPICE indicate that the proposed model outperform the existing models in terms of power and delay. Moreover, using load-transistor results in 48.23% reductions in terms of power-delay-product (PDP) compared with the best model ever observed. Furthermore, the implementation of ternary arithmetic circuits such as half adder and multiplier using load-transistor has been investigated. An added common term between Sum and Carry output in half-adder (HA) and Carry and Product output in lower multiplier (MUL) has been used in arithmetic circuits. Considering the fact that a better proposal with higher performance has been utilized for the implementation of three-valued gates, our model results in the reduction of 9.95% and 23.87% PDP in HA and MUL respectively compared with the best models observed.