The design and realization of a new high speed FPGA-based chaotic true random number generator. (February 2017)

• Record Type: Journal Article
• Authors: Koyuncu, İsmail; Turan Özcerit, Ahmet
• Is Part Of: Computers & electrical engineering. Volume 58(2017)
• Page Start: 203
• Page End: 214
• Publication Date: 2017-02
• Subjects: Chaos -- Chaotic oscillators -- Field programmable gate array -- RK4 algorithm -- True random number generator -- NIST-800-22 statistical tests; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2016.07.005
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: Sundarapandian–Pehlivan chaotic system (SPCS) has been modeled and simulated in three distinct platforms (Numerical, Pspice and FPGA-based). SPCS has been modeled in VHDL language by using RK4 algorithm and has been synthesized for Xilinx Virtex-6 FPGA chip in development environment. The maximum operation frequency of FPGA-based chaotic system is 293.815 MHz and the system can calculate 1, 000, 000 data in 0.201 s. The high speed TRNG model has been implemented on an FPGA using SPCS and the maximum operating frequency has been achieved as 293 MHz with a speed of 58.76 Mbit/s. Proposed new TRNG can be run as fast as been verified by two statistical based standards, FIPS-140-1 and NIST-800-22. Abstract: Chaotic systems and chaos-based applications have been commonly used in the fields of engineering recently. The most essential part of them is the chaotic oscillator that has very critical role in some applications such as chaotic communications and cryptography. In this study, Sundarapandian–Pehlivan chaotic system has been modeled and simulated in three distinct platforms to show the advantages of FPGA-based chaotic oscillator with respect to alternative solutions. In the first stage, the chaotic system has been modeled numerically by the help of fourth order of Runge–Kutta (RK4) method. Additionally, phase portraits of the system have been obtained and Lyapunov exponents have been examined. Secondly, the system has been modeled by using PSpice for the implementation of the chaotic system with analog circuit elements. Then, Pspice simulation results have been compared with the numerical outcome to justify the designed model. Furthermore, the chaotic system has been physically confirmed with real analog circuit elements. Signals obtained from the physical system have been verified with both numerical and PSpice results. It has been also modeled by the help of method of RK4 in a hardware description language (VHDL) and the model further has been synthesized and tested for Xilinx Virtex-6 FPGA chip. Finally, the chaotic oscillator designed has been tested for True Random Number Generators (TRNG) and the maximum operating frequency has been achieved as 293 MHz with a speed of 58.76 Mbit/s. Besides, the random bit sets produced by TRNG have been further verified by FIPS-140-1 and NIST-800-22 statistical standards and it has been proved that the proposed design can be used in embedded cryptologic applications.