Performance analysis of pre-equalized multilevel partial response modulation for high-speed electrical interconnects. (February 2017)

• Record Type: Journal Article
• Authors: Guenach, M.; Jacobs, L.; Kozicki, B.; Moeneclaey, M.
• Is Part Of: Computers & electrical engineering. Volume 58(2017)
• Page Start: 30
• Page End: 48
• Publication Date: 2017-02
• Subjects: High-speed electrical interconnects -- Modulation -- Partial response -- Equalization -- Error probability bounds; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2016.12.010
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: In this paper, we first review the baseband modulation techniques intended for use in short-reach, high-speed electrical interconnects. Then we briefly introduce the high-level design concepts of the investigated electrical interconnect, indicating the main limitations and outlining the transceiver complexity related to the advanced modulation designs. We further investigate finite-complexity linear pre-equalization under an average transmit power constraint of both full-response and precoded partial response signaling with pulse amplitude modulation ( L -PAM) mapping. For a representative electrical interconnect, we argue that the constellation size, the type of modulation, the detection method as well as the number of pre-equalizer taps should be carefully selected in order to achieve target error performance at data rates between 100 Gbit/s and 200 Gbit/s. We show that for many combinations of above mentioned parameters, precoded duobinary 4-PAM yields the best error performance for a fixed average transmit power.