A survey of techniques for architecting TLBs. (22nd December 2016)

• Record Type: Journal Article
• Authors: Mittal, Sparsh
• Is Part Of: Concurrency and computation. Volume 29:Number 10(2017)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2016-12-22
• Subjects: classification -- power management -- prefetching -- Review -- superpage -- TLB -- virtual cache -- workload characterization; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.4061
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Translation lookaside buffer (TLB) caches virtual to physical address translation information and is used in systems ranging from embedded devices to high‐end servers. Because TLB is accessed very frequently and a TLB miss is extremely costly, prudent management of TLB is important for improving performance and energy efficiency of processors. In this paper, we present a survey of techniques for architecting and managing TLBs. We characterize the techniques across several dimensions to highlight their similarities and distinctions. We believe that this paper will be useful for chip designers, computer architects, and system engineers.