Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis. (April 2017)

• Record Type: Journal Article
• Authors: Neagu, Mădălin; Manich, Salvador
• Is Part Of: Microelectronics journal. Volume 62(2017)
• Page Start: 85
• Page End: 98
• Publication Date: 2017-04
• Subjects: Data scrambling -- Cache memories -- Differential power analysis -- Side-channel attack -- Error correction; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.02.010
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Some algorithms running with compromised data select cache memory as a type of secure memory where data is confined and not transferred to main memory. However, cold-boot attacks that target cache memories exploit the data remanence. Thus, a sudden power shutdown may not delete data entirely, giving the opportunity to steal data. The biggest challenge for any technique aiming to secure the cache memory is performance penalty. Techniques based on data scrambling have demonstrated that security can be improved with a limited reduction in performance. However, they still cannot resist side-channel attacks like power or electromagnetic analysis. This paper presents a review of known attacks on memories and countermeasures proposed so far and an improved scrambling technique named random masking interleaved scrambling technique (RM-ISTe). This method is designed to protect the cache memory against cold-boot attacks, even if these are boosted by side-channel techniques like power or electromagnetic analysis.