Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET. (April 2017) - Es-Sakhi, Azzedin; Chowdhury, Masud
Abstract: This paper presents a study of the structure and the characteristics of the emerging device - SOI-FinFET. Close form models are developed to estimate the values of the device capacitances. Using these capacitance models, an expression for subthreshold swing of the SOI-FinFET is derived. These models have been used to investigate the behavior of SOI-FinFET in the subthreshold region, the I-V characteristics, and the drain induced barrier lowering (DIBL). These approximations are based on the structure and the internal capacitive coupling of SOI-FinFET. The effects of doping attenuation in the channel, charge trapping in the insulator, and some other factors are not taken into consideration, because the focus of this paper is to investigate the impact of the geometric dimensions and related factors on the behavior and the operation of SOI-FinFET. The channel of SOI-FinFET is either undoped or lightly doped. In addition to analyzing the impact of various geometric parameters on the behavior of the device, the developed models and the presented analysis would be of great importance for future CAD tool development and design automation. It is observed that by optimizing these dimensional factors, a subthreshold swing (S) value very close to 60 mV/decade can be achieved for SOI-FinFET. Graphical abstract: Highlights: Modeling and evaluation of the intrinsic capacitance components of SOI-FinFET. Analytical approach to model and estimate the subthreshold swing of SOI-FinFET. The aspect ratio Fin-height/Fin-width (AR) can be improved for ULP applications. High AR the transistor effective area increases, which enhance driving capability. A high aspect ratio will give a lower DIBL and lower subthreshold swing.