Design of impedance matching circuits for RF energy harvesting systems. (April 2017)

• Record Type: Journal Article
• Authors: Hameed, Zohaib; Moez, Kambiz
• Is Part Of: Microelectronics journal. Volume 62(2017)
• Page Start: 49
• Page End: 56
• Publication Date: 2017-04
• Subjects: CMOS -- Modeling -- Matching -- High-frequency impedance -- Calculations -- Low power design -- Analysis; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.02.004
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a systematic design methodology for impedance matching circuits of an RF energy harvester to maximize the harvested energy for a range of input power levels with known distribution. Design of input matching networks for RF rectifier differs from those for traditional RF circuits such as low-noise amplifier because the transistors in the RF rectifiers operate in different regions. In this work, it is shown that the input impedance of the rectifier estimated based on small signal simulation of transistors at the peak of input signal in the rectifier when the transistors are biased with stable DC operating voltage provides the largest harvested energy from a fixed input power. For variable input power levels, a matching network selection strategy is proposed to maximize expected harvested energy given the probability density distribution of input power levels. As an experimental sample, an RF energy harvester circuit is designed to maximize the harvested energy in the 902–928 MHz band employing an off-chip impedance matching circuit designed using the proposed methodology. The proposed RF energy harvester exhibits a measured maximum power conversion efficiency (PCE) of 32% at −15 dBm (32 μW) and delivers an output DC voltage of 3.2 V to a 1 MΩ load.