Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI. (April 2017) - Johannah, J. Jeba; Korah, Reeba; Kalavathy, Maria; Sivanandham,
Abstract: Scaling down of CMOS Technology reduces supply voltage which helps evade device botch caused by high electric fields in the conducting channel under the gate and gate oxide. Voltage scaling lessens circuit power consumption but increases delay of logic gates badly and the performance is degraded to a large extent in deep submicron CMOS VLSI circuits. In order to achieve good performance, the delay of logic gates has to be decreased. Circuits for trimming down of leakage power in sub-micron technologies also increase the dynamic power to a large extent. In this paper, a novel hybrid MTCMOS technique is proposed to reduce the enormous delay in gates due to sleep transistors; also, static power consumption is reduced without much affecting the dynamic power consumption of the circuit. For the 16-bit Ripple Carry Adder, the proposed technique can save up to 76.8% of static power consumption and 55.5% of dynamic power consumption also. Graphical abstract: Highlights: Addition of high threshold voltage or low threshold voltage transistor(s) in gates. Enhanced performance of gates in deep sub-micron CMOS. Very high static power minimization in Nano technology. Full output voltage swing.