A design of 10-bit, 10 MS/s Pipelined ADC with Time-interleaved SAR. (April 2017) - Jang, ByeongGi; Hayder, Abbas Syed; Do, SungHan; Cho, SungHun; Lee, DongSoo; Pu, YoungGun; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon
Abstract: This paper presents a 10-bit, 10 MS/s pipelined ADC with a time-interleaved SAR. Owing to the shared multiplying-DAC between the flash ADC and the multi-channel-SAR ADC, the total capacitance of the SAR ADC is decreased by 93.75%. The proposed ADC architecture can therefore provide a higher resolution than the conventional time-interleaved flash-SAR ADC. The proposed 10-bit, 10 MS/s ADC achieves a 9.318-bit ENOB and a figure-of-merit of 357.11 fJ/conversion-step. The ADC that consumes 2.28 mW under a supply voltage of 1.2 V was fabricated in 0.13 µm CMOS and occupies an area of only 0.21 mm 2 .