Efficient hardware implementation of radial basis function neural network with customized-precision floating-point operations. (March 2017) - Ayala, Helon Vicente Hultmann; Muñoz, Daniel M.; Llanos, Carlos H.; Coelho, Leandro dos Santos
Abstract: This paper aims at the proposition of novel architectures for radial basis function neural networks implementation on hardware with custom-precision floating-point operations for black-box system modeling. An analysis tool was built to establish the trade-off between the consumption of hardware resources and the precision of the outputs, on the basis of the usage of the logic blocks on a field-programmable gate array and output quality. The architectures have been tested with a standard system identification benchmark and the speedup factors, when compared to a C implementation, are on the order of hundreds, what shows the importance of ad-hoc hardware architectures for improving computational efficiency. Abstract : Highlights: Two hardware architectures with custom floating-point operation for RBFNN are given. The full-parallel architecture is the fastest by using more hardware resources. The shared-neurons architecture optimizes hardware resources. The architectures are applied to nonlinear black-box system identification. Speedup in the order of hundreds are obtained when compared to C implementation.