A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in ΔΣ fractional-N PLL frequency synthesizer. (March 2017)

• Record Type: Journal Article
• Authors: Hati, Manas Kumar; Bhattacharyya, Tarun Kanti
• Is Part Of: Microelectronics journal. Volume 61(2017)
• Page Start: 21
• Page End: 34
• Publication Date: 2017-03
• Subjects: Fractional-N PLL frequency synthesizer -- Loop bandwidth calibration -- Automatic frequency control (AFC) -- Frequency to digital conversion (FDC) -- Frequency resolution of the FDC (KVFC) -- Frequency resolution of the loop bandwidth calibration (KLBC); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.12.014
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This work presents the design of a Δ Σ fractional-N PLL frequency synthesizer with a new loop bandwidth calibration and automatic frequency control (AFC) circuit, applicable for wide band RF communication system. This new and unique loop bandwidth calibration circuit has been implemented using logarithmic and anti-logarithmic (Base2) architecture. This architecture is an efficient design technique as well as faster operation in CMOS domain. The operating frequency range of the Δ Σ fractional-N PLL frequency synthesizer is from 2.158 to 5.133 GHz. The variation of LC VCO gain ( K VCO ) is obvious due to wide band application and it varies from 30.65 MHz/Volt to 368 MHz/Volt for the frequency range of 2.158–5.133 GHz. Constant loop bandwidth is maintained by controlling the charge pump current. Power consumption of the Δ Σ fractional-N PLL frequency synthesizer is 34 mW from a 1.2 Volt power supply and the work has been carried out in 0.13 μm standard CMOS process. Also, this design includes an automatic frequency control unit for the LC VCO circuit which is coarsely tuned within 1.825 μs for K VFC =10 for worst case condition and it completes the loop bandwidth (LBW) calibration within 7.84 μs for K LBC =150 for worst case condition. The maximum locking time of the Δ Σ fractional-N PLL frequency synthesizer with loop bandwidth calibration and automatic frequency control circuit is 12.7 μs for K VFC = 10 and K LBC = 150 for worst case condition. The Δ Σ fractional-N PLL is locked much faster than any work reported earlier using the proposed PFD, CP, proposed pulse swallow divider, efficient AFC circuit for LC VCO and a new loop BW calibration technique in transistor level simulation using Cadence SpectreRF. The main advantage of this loop bandwidth calibration technique is that the calibration time can be adjusted according to the PLL output frequency, loop bandwidth calibration accuracy and tuning frequency range of the LC VCO.