Effective method to improve linearity of high-resolution SAR ADC. (March 2017)

• Record Type: Journal Article
• Authors: Fan, Hua
• Is Part Of: Microelectronics journal. Volume 61(2017)
• Page Start: 35
• Page End: 42
• Publication Date: 2017-03
• Subjects: Analog-to-digital converter(ADC) -- Successive Approximation Register(SAR) ADC -- Capacitive digital-to-analog converter(DAC) -- DNL -- INL; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.12.010
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This work proposes one DAC switching technique for successive approximation register (SAR) analog-to-digital converter (ADC), cycling&averaging technique. The proposed cycling&averaging technique can reduce the noise and harmonic distortion caused by capacitor mismatch without trimming or complicated least-mean-square(LMS) digital calibration. The application of the cycling&averaging technique to two kinds of 12-bit SAR ADC is demonstrated by 1000 Monte-Carlo runs, in which the capacitor mismatch for every capacitor is randomly generated for one thousand times. Simulation results show that the method improves the differential non-linearity (DNL) from 1.45 LSB to 0.47 LSB and the integral non-linearity (INL) from 1.87 LSB to 0.48 LSB with a standard deviation of 4%. Further, the SFDR is more than 10 dB better. Meanwhile, the schemes proposed require only small additional circuit on a typical SAR ADC configuration, which are more feasible to implement high-resolution SAR ADC compared with the traditional calibration schemes.