Trivium hardware implementations for power reduction. (7th November 2016)

• Record Type: Journal Article
• Authors: Mora‐Gutiérrez, J. M.; Jiménez‐Fernández, C.J.; Valencia‐Barrero, M.
• Other Names: Acosta Antonio guestEditor.; Addabbo Tommaso guestEditor.
• Is Part Of: International journal of circuit theory and applications. Volume 45:Number 2(2017:Feb.)
• Page Start: 188
• Page End: 198
• Publication Date: 2016-11-07
• Subjects: Trivium -- stream cipher -- low power -- lightweight cryptography -- hardware implementation; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2281
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non‐linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low‐power Trivium designs were implemented and characterized in 350‐nm standard‐cell technology with both transistors and gate‐level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area. Copyright © 2016 John Wiley & Sons, Ltd. Abstract : This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. The proposed low‐power Trivium designs were implemented and characterized in standard‐cell technology with both transistors and gate‐level models, in order to permit both electrical and logical simulations. The results show decreased average power consumption by between 15% and 25%.