A dedicated private‐shared cache design for scalable multiprocessors. (12th May 2016)

• Record Type: Journal Article
• Authors: Cebrián, Juan M.; Fernández‐Pascual, Ricardo; Jimborean, Alexandra; Acacio, Manuel E.; Ros, Alberto
• Other Names: Grosu Daniel guestEditor.; Jin Hai guestEditor.; Maheshwari Ketan guestEditor.; Katz Daniel guestEditor.; Olabarriaga Silvia D. guestEditor.; Wozniak Justin guestEditor.; Thain Douglas guestEditor.
• Is Part Of: Concurrency and computation. Volume 29:Number 2(2017)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2016-05-12
• Subjects: Coherence protocols -- private data -- shared data -- separate caches; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.3871
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Most modern architectures are based on a shared‐memory design. Correctness of these architectures is ensured by means of coherence protocols and consistency models. However, performance and scalability of shared‐memory systems is usually constrained by the amount and size of the messages used to keep the memory subsystem coherent. This is not only important in high performance computing, but also in low power embedded systems, specially if coherence is required between different components of the system‐on‐chip. We argue that using the same mechanism to keep coherence for all memory accesses can be counterproductive, because it incurs unnecessary overhead for data addresses that would remain coherent after the access (i.e., private data and read‐only shared data). This paper proposes the use of dedicated caches for two different kinds of data (i) data that can be accessed without contacting other nodes and (ii) modifiable shared data. The private cache (L1P) will be independent for each core and will store private data and read‐only shared data. On the other hand, the shared cache (L1S), will be logically shared but physically distributed for all cores. With this design, we can significantly simplify the coherence protocol, reduce the on‐chip area requirements and reduce invalidation time. However, this dedicated cache design requires a classification mechanism to detect the nature of the data that is being accessed. Results show two drawbacks to this approach: first, the accuracy of the classification mechanism has a huge impact on performance. Second, a traditional interconnection network is not optimal for accessing the L1S, increasing register‐to‐cache latency when accessing shared data. Copyright © 2016 John Wiley & Sons, Ltd.