Analytical modeling of the lattice and thermo-elastic coefficient mismatch-induced stress into silicon nanowires horizontally embedded on insulator-on-silicon substrates. (January 2017) - Chatterjee, Sulagna; Chattopadhyay, Sanatan
Abstract: In the current work, an analytical model has been developed to estimate the amount of induced stress in nanowires which are horizontally embedded with different fractions within an Insulator-on-Silicon substrate. For estimating such stress, different crystallographic orientations of substrates and embedded nanowires have been considered. The induced stress for both the difference in thermo-elastic constants and lattice-mismatch is included and accuracy of the analytical model has been verified with the similar results obtained from ANSYS Multiphysics. Induced stress is observed to be insensitive of the nanowire size, however, depends significantly on the fractional insertion of the nanowires. A tensile stress of 1.95 GPa and a compressive stress of −1.0719 GPa have been obtained for the 〈100〉 oriented Si-nanowires. Hole mobility of 850 cm 2 /Vs can be achieved for the 3/4th insertion of the nanowires which is comparable to electron mobility and therefore can be utilized for the design of symmetric nano-electronic devices. Graphical abstract: Highlights: Analytical calculation of substrate- and process-induced stress is developed for partially embedded nanowires. Induced stress is estimated for different fractional insertions and orientations of horizontal nanowires. Hole and electron mobility have been made equal by engineering fractions of insertion within the insulating layer.