A physical unclonable function based on a 2‐transistor subthreshold voltage divider. (18th November 2016)

• Record Type: Journal Article
• Authors: De Rose, Raffaele; Crupi, Felice; Lanuzza, Marco; Albano, Domenico
• Other Names: Acosta Antonio guestEditor.; Addabbo Tommaso guestEditor.
• Is Part Of: International journal of circuit theory and applications. Volume 45:Number 2(2017:Feb.)
• Page Start: 260
• Page End: 273
• Publication Date: 2016-11-18
• Subjects: CMOS design -- physical unclonable functions (PUFs) -- subthreshold operation -- variability -- analog design -- hardware security; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2282
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: In this paper, a compact circuit solution for silicon‐based static physical unclonable functions (PUFs) is presented. The proposed solution exploits the variability of a simple voltage divider, implemented by two identical series‐connected nMOSFETs in a commercial 65‐nm CMOS process, to generate a random and stable nanokey. Both the transistors are biased in the subthreshold regime to enhance the output voltage dispersion and consequently the variability of the PUF response. The bit key generation is obtained by comparing the analog outputs of a pair of voltage dividers. Monte Carlo simulations on 10, 000 samples have been performed to deduce the design guidelines for transistor sizing aimed at ensuring a high robustness of the PUF response against noise, supply voltage, and temperature variations. When compared with some state‐of‐the‐art PUF designs, the proposed circuit solution proves to be a promising and competitive candidate for implementing analog and static PUFs featuring small area occupancy, low‐power features, and high reliability. Copyright © 2016 John Wiley & Sons, Ltd. Abstract : This paper focuses on an extremely compact CMOS solution for implementing silicon‐based analog and static physical unclonable functions (PUFs). The proposed solution is based on pairs of two‐transistor voltage dividers, each consisting of a series of two identical nMOSFETs that operate in the subthreshold regime with the aim of emphasizing the random process fluctuations. Consequently, the proposed PUF exhibits a high variability and a good robustness against noise, supply voltage, and temperature variations when compared with some state‐of‐the‐art PUF designs.