A low phase noise V‐band 40 NM CMOS phase locked loop for wireless communication. Issue 2 (February 2017)

• Record Type: Journal Article
• Authors: Zhou, Qian; Han, Yan; Zhang, Shifeng; Han, Xiaoxia; Jie, Lu; Cheung, Ray C. C.; Feng, Guangtao
• Is Part Of: Microwave and optical technology letters. Volume 59:Issue 2(2017:Feb.)
• Page Start: 278
• Page End: 283
• Publication Date: 2017-02
• Subjects: V‐band PLL -- low phase noise -- mutual injection locking; Microwaves -- Periodicals; Optics -- Periodicals; 621
• DOI: 10.1002/mop.30289
• Languages: English
• ISSNs: 0895-2477

Abstract

ABSTRACT: This letter presents a V‐band phase‐locked loop (PLL) that employs mutual injection‐locking voltage controlled oscillator (VCO) and zero blind zone phase frequency detector (PFD) to enhance phase noise performance. This architecture is physically implemented in 40nm CMOS process with a die area of 0.7 mm 2 . The silicon results demonstrate an in‐band phase noise of −90dBc/Hz at 500 kHz offset and −92dBc/Hz at 1MHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:278–283, 2017