Comprehensive understanding of dark count mechanisms of single-photon avalanche diodes fabricated in deep sub-micron CMOS technologies. (March 2017) - Xu, Yux; Xiang, Ping; Xie, Xiaopeng
Highlights: The dark count noise mechanisms of DSM CMOS SPADs are investigated. A field dependence of DCR model including SRH, TAT and BTBT mechanisms is derived. Each DCR component is calculated using key model parameters from TCAD simulation. The TAT tunneling is the main DCR source for SPAD devices in DSM CMOS technologies. The BTBT tunneling will be the dominant origin of DCR for the scaled DSM CMOS SPADs. Abstract: The dark count noise mechanisms of single-photon avalanche diodes (SPADs) fabricated in deep sub-micron (DSM) CMOS technologies are investigated in depth. An electric field dependence of tunneling model combined with carrier thermal generation is established for dark count rate (DCR) prediction. Applying the crucial parameters provided by Geiger mode TCAD simulation such as avalanche triggering probability and electric field distribution in the SPAD avalanche region, the individual contribution of each noise source to DCR is calculated for several SPADs in DSM CMOS technologies. The model calculation results reveal that the trap-assisted tunneling is the main DCR generation source for these DSM CMOS SPADs. With the increase of doping levels in the device avalanche region, the band-to-band tunneling will be the dominant factor that could lead to the higher DCR in scaled DSM CMOS technologies.