A survey of techniques for designing and managing CPU register file. (13th July 2016)

• Record Type: Journal Article
• Authors: Mittal, Sparsh
• Is Part Of: Concurrency and computation. Volume 29:Number 4(2017)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2016-07-13
• Subjects: review -- classification -- CPU -- register file -- heterogeneous bank design -- power management -- soft‐error resilience; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.3906
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Processor register file (RF) is an important microarchitectural component used for storing operands and results of instructions. The design and operation of RF have crucial impact on the performance, energy efficiency, and reliability of the processor, and hence, several techniques have been recently proposed to manage RF in modern processors. In this paper, we present a survey of techniques for architecting and managing CPU register file. We classify the techniques across several parameters to underscore their similarities and differences. We hope that this paper will provide insights to researchers into working of RF and inspire even more efforts towards optimization of RF in next‐generation computing systems. Copyright © 2016 John Wiley & Sons, Ltd.