Analysis of feedback predictive encoder based ADCs. Issue 1 (3rd January 2017)

• Record Type: Journal Article
• Authors: Scanlan, Anthony; O'Hare, Daniel; Halton, Mark; O'Brien, Vincent; Mullane, Brendan; Thompson, Eric
• Is Part Of: Compel. Volume 36:Issue 1(2017)
• Page Start: 129
• Page End: 152
• Publication Date: 2017-01-03
• Subjects: Electronics -- Circuit analysis -- Predictive techniques -- Microelectronics; Electrical engineering -- Data Processing -- Periodicals; Electrical engineering -- Mathematics -- Periodicals; Electrical engineering -- Periodicals; Electronics -- Data Processing -- Periodicals; Electronics -- Mathematics -- Periodicals; 621.3
• DOI: 10.1108/COMPEL-12-2015-0464
• Languages: English
• ISSNs: 0332-1649

Abstract

Abstract : Purpose: The purpose of this paper is to present analysis of the feedback predictive encoder-based analog-to-digital converter (ADC). Design/methodology/approach: The use of feedback predictive encoder-based ADCs presents an alternative to the traditional two-stage pipeline ADC by replacing the input estimate producing first stage of the pipeline with a predictive loop that also produces an estimate of the input signal. Findings: The overload condition for feedback predictive encoder ADCs is dependent on input signal amplitude and frequency, system gain and filter order. The limitation on the practical usable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum usable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimization of the power consumption. Practical implications: A practical switched capacitor implementation of the predictive encoder-based ADC is proposed. The power consumption of key circuit blocks is investigated. Originality/value: This paper presents a methodology to optimize the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimization of power consumption based on the allocation of time between the gain stage and the successive approximation register ADC operation is investigated. The lower bound of power consumption for this architecture is estimated.