A novel design and implementation technique for low complexity variable digital filters using multi-objective artificial bee colony optimization and a minimal spanning tree approach. (March 2017)

• Record Type: Journal Article
• Authors: Bindima, T.; Elias, Elizabeth
• Is Part Of: Engineering applications of artificial intelligence. Volume 59(2016:Nov.)
• Page Start: 133
• Page End: 147
• Publication Date: 2017-03
• Subjects: Artificial bee colony (ABC) -- Canonic signed digit -- Minimal spanning tree -- Multi-objective ABC -- Shift inclusive differential coefficients -- Variable digital filters; Engineering -- Data processing -- Periodicals; Artificial intelligence -- Periodicals; Expert systems (Computer science) -- Periodicals; Ingénierie -- Informatique -- Périodiques; Intelligence artificielle -- Périodiques; Systèmes experts (Informatique) -- Périodiques; Artificial intelligence; Engineering -- Data processing; Expert systems (Computer science); Periodicals; 620.00285
• DOI: 10.1016/j.engappai.2016.12.011
• Languages: English
• ISSNs: 0952-1976

Abstract

Abstract: Farrow structure in canonic signed digit (CSD) space is an efficient approach for the design of real-time tunable finite precision variable digital filters (VDFs). A novel design method for Farrow structure based VDFs in CSD space with reduced hardware complexity is proposed in this paper. The design approach makes use of the multi-objective artificial bee colony (MOABC) optimization algorithm with an integer search space to find the optimal Farrow sub-filter coefficients. Further, a novel low complexity implementation approach for the finite precision VDF using a minimal spanning tree approach is also proposed. The minimal spanning tree approach deploys the shift inclusive differential coefficients (SIDCs) and the different shifted SIDCs with common sub-expression elimination (CSE) to optimize the multiple constant multiplications involved in the filter realization. The attractive feature of our proposed method using MOABC and SIDCs with CSE lies in the increased hardware complexity reduction of the VDFs, compared to the existing methods, which in turn reduces the hardware resource utilization and power consumption drastically compared to the continuous coefficient VDFs. The hardware implementation of the VDF using the proposed method has also been done using Xilinx ISE to analyse the reduction in the hardware complexity and dynamic power.