A comparative design study of continuous‐time incremental sigma‐delta ADC architectures. (15th May 2016)

• Record Type: Journal Article
• Authors: Tao, Sha; Rusu, Ana
• Is Part Of: International journal of circuit theory and applications. Volume 44:Number 12(2016:Dec.)
• Page Start: 2147
• Page End: 2163
• Publication Date: 2016-05-15
• Subjects: A/D conversion -- incremental sigma‐delta -- continuous‐time -- extended‐range -- two‐step; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2218
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: This paper presents a comparative design study of continuous‐time (CT) incremental sigma‐delta (IΣΔ) ADCs, which can expand another dimension of the IΣΔ ADC world that is dominated by discrete‐time implementations. Several CT IΣΔ ADC architectures are introduced and analyzed aiming to reduce the modulator's sampling frequency and consequently the power dissipation. Based on the analytical results, three CT IΣΔ ADCs are selected to be examined, implemented, and tested. The three ADC prototypes, fabricated in a standard 0.18‐m CMOS technology, demonstrate competitive figure‐of‐merits in terms of power efficiency compared to the state‐of‐the‐art counterparts. Copyright © 2016 John Wiley & Sons, Ltd. Abstract : This paper presents a comparative design study of continuous‐time (CT) incremental sigma‐delta (IΣΔ) ADCs, which can expand another dimension of the IΣΔ ADC world that is dominated by discrete‐time implementations. Several CT IΣΔ ADC architectures are introduced and analyzed aiming to reduce the modulator's sampling frequency and consequently the power dissipation. Based on the analytical results, three CT IΣΔ ADCs are selected to be examined, implemented, and tested.