A low-power SHA-3 designs using embedded digital signal processing slice on FPGA. (October 2016)

• Record Type: Journal Article
• Authors: Kundi, Dur-e-Shahwar; Aziz, Arshad
• Is Part Of: Computers & electrical engineering. Volume 55(2016)
• Page Start: 138
• Page End: 152
• Publication Date: 2016-10
• Subjects: Cryptography -- Secure hash algorithm-3 (SHA-3) -- Field programmable gate array (FPGA) -- Keccak -- DSP48E slice -- Logical cascade structure (LCS); Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2016.04.004
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: Two low-power SHA-3 designs are provided on UltraScale FPGA using its embedded Digital Signal Processing (DSP) slice; one for the area constrained environments and the other for high-speed applications. All bitwise logical operations of SHA-3 are logically grouped in 48-bit wide parallel operations to get maximum benefit of Xilinx DSP48E2 slice structure. Logical Cascade Structure (LCS) strategy is used to confine maximum SHA-3 logic within same DSP slice column and also to get maximum benefit from its low-power dedicated interconnect. The DSP based compact SHA-3 design utilizes 79.10% less DSP slices and consumes only 1/7th of power while high-speed 1600-bit design provides 23.57 Gbps with consumption of only 1/5th of power. Graphical abstract: Abstract: This work presents two low-power Secure Hash Algorithm-3 (SHA-3) designs on Field Programmable Gate Array (FPGA) using embedded Digital Signal Processing (DSP48E) slice, one for area constrained environments and the other for high-speed applications. The seven equations of SHA-3 are logically optimized to three and four stage pipelined organizations for our compact and high-speed designs, respectively. The maximum parallelism between all the bitwise operations of different stages of SHA-3 is explored with respect to the 48-bit structure of DSP slice. Further Logical Cascade Structure (LCS) design strategy is proposed in accordance with the DSP slice organization. These optimizations result in saving of resources and at the same time achieve low-power with high performance. Our compact design results in saving of 79.10% DSP slices and consumes only 1/7 th of power while 1600-bit DSP design provides 23.57 Gbps throughput and consumes only 1/5 th of power as compared to the conventional SHA-3 designs.