Multiplexed stego path on reconfigurable hardware: A novel random approach. (October 2016)

• Record Type: Journal Article
• Authors: Ramalingam, Balakrishnan; Amirtharajan, Rengarajan; Rayappan, John Bosco Balaguru
• Is Part Of: Computers & electrical engineering. Volume 55(2016)
• Page Start: 153
• Page End: 163
• Publication Date: 2016-10
• Subjects: Steganography -- LSB substitution -- Reconfigurable hardware architecture -- FPGA; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2016.02.010
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Information security, though having different areas of interest, is fairly specific and confined to secure digital data transmission. Currently, there are many data security techniques addressing various aspects of secured information sharing. Amongst those, one that is sufficiently epic, successful and challenging is steganography. This paper proposes a robust adaptive image steganography scheme titled the adaptive random inverted key LSB substitution technique, which combines steganography and cryptography to enhance the security of confidential data and imperceptibility of the stego object. FPGA implementation of the steganography technique provides massively parallel operations, perfect shielding against infectious attacks and ease of embedding as a low-power hardware accelerator in mobile computing systems. Hence, the proposed algorithm is implemented on a Cyclone II FPGA. The synthesized result demonstrates that the FPGA architecture yields a throughput of 441.38 Mbps for data embedding and 914.29 Mbps for data extraction.