The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology. (December 2016) - Halak, Basel; Tenentes, Vasileios; Rossi, Daniele
Abstract: On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are much more robust to BTI aging degradation. To the best of our knowledge, this is the first work addressing the effects of BTI on the the delay and power consumption of level shifters. Highlights: Comprehensive analysis of BTI effect on level shifters used in multi-Vdd domains. Standard low-to-high level shifter suffers from very high performance degradation. This degradation is much higher than that experienced by standard CMOS logic gates. This is attributed to differential signaling structure of level shifters. This additional delay must be accounted for by margin based design approaches.