Rail to rail radiation hardened operational amplifier in standard CMOS technology with standard layout techniques. (December 2016) - Agostinho, Peterson R.
Abstract: This work presents a rail-to-rail operational amplifier hardened by design against ionizing radiation at circuit level, using only standard layout techniques. Not changing transistor layout, for instance by using enclosed layout structures, allows design and simulation using the standard models provided by the foundry. The circuit was fabricated on a standard 0.35 μm CMOS process, and submitted to a total ionizing dose (TID) test campaign using a 60 Co radiation source, at a dose rate of 0.5 rad(Si)/s, reaching a final accumulated dose of 500 krad(Si). The circuit proved to be radiation tolerant for the tested accumulated dose. The design practices used to mitigate TID effects are presented and discussed in detail. Highlights: A CMOS op-amp robust to an accumulated TID of 500 krad(Si) is presented. A circuit hardened by design against ionizing radiation at circuit level. TID tolerance was obtained avoiding the use of any enclosed layout transistor. VTH mismatch due to TID is the most relevant issue on the performances.