A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnology. (December 2016)

• Record Type: Journal Article
• Authors: Abiri, Ebrahim; Darabi, Abdolreza
• Is Part Of: Microelectronics journal. Volume 58(2016)
• Page Start: 44
• Page End: 59
• Publication Date: 2016-12
• Subjects: Gate Diffusion Input (GDI) Technique -- Carbon Nano Tube (CNT) Field Effect Transistor (CNTFET) -- Multiple-Valued Logic (MVL) -- Ternary logic -- Process and temperature variations -- Static Noise Margin (SNM) -- Power-Delay Product (PDP); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.10.009
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The conventional complementary metal-oxide semiconductor (CMOS) design techniques confront to the limitation of designing the integrated circuits (ICs), especially memories, with multiple-valued logic (MVL) in nanotechnology. Gate diffusion input (GDI) technique, provides the possibility to design low power logic gates with small chip area and interconnection capacitors while the number of transistors is diminished. In this paper first ternary GDI (t-GDI) cell based on the proposed binary (two-valued) modified GDI (m-GDI) method, which is appropriate for designing circuits using MVL, is designed. Then, by using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better noise margins and also small standard deviation of results, first novel design of a ternary SRAM (T-SRAM) cell is presented for nano process, which has smaller standby power dissipation and standard deviation for delay of writing and reading cycles, better read static noise margin (RSNM) and lower signal control complexity. The design of specific structure of 4-words×4-bits, ternary SRAM (4×4 T-SRAM) shows that the number of connections, chip area is decreased and power-delay product (PDP) criterion is improved for writing and reading cycles with significant small standard deviation in compare with the other similar T-SRAMs designed. The effects of different process variations such as density, number of CNTs and temperature variations are extensively evaluated by Monte-Carlo simulation, with respect to performance metrics such as delay, power dissipation and PDP of writing and reading cycles, also RSNM parameter for SRAM cells. The comparison exhibits that in all cases the proposed T-SRAM cell showing a substantial small standard deviation and considerable lower variability percentage than state-of-the art SRAM cells. So, the proposed T-SRAM cell design has the lowest sensitivity variations, thus it is an attractive choice for nano technology application in the presence of impact process and temperature variations. The simulation is done with Synopsys H-SPICE simulator in 32 nm technology under the condition of variations.