On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology. (September 2016) - Viale, B.; Fer, M.; Courau, L.; Galy, P.; Allard, B.
Abstract: The need for a novel multi-scale ESD (ElectroStatic Discharge) network recognition and verification methodology is described in this paper. The proposed solution is used to limit the risk of ESD design errors and to enhance IC reliability, independently of the implemented ESD protection strategy and the type of package assembly technique. This method relies on a topology-aware & graph-based verification paradigm which is generic enough to be usable at every step of the design flow. Its efficiency is illustrated with examples involving custom I/O ring portions in 28nm UTBB FD-SOI High-K metal gate technology. Highlights: A method to identify and verify on-chip ESD protection networks is described. The robustness of the method is tested on two cases involving different ESD protection strategies. The ESD network overview is given in the form of a directed graph. ESD path existence results are summarized in the form of a test-plan matrix.