FPGA Implementation of Area-Efficient IEEE 754 Complex Divider. (2016)

• Record Type: Journal Article
• Authors: Varghese, Anila Ann; Pradeep, C.; Eapen, Madhuri Elsa; Radhakrishnan, R.
• Is Part Of: Procedia technology. Volume 24(2016)
• Page Start: 1120
• Page End: 1126
• Publication Date: 2016
• Subjects: Complex Division -- FPGA -- IEEE754 -- Module Reuse; Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.05.245
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: Division algorithms are less often used unlike other arithmetic operations. But it cannot be avoided in some systems to achieve some functionality. The division of complex numbers has got applications in fields like telecommunication, microwave systems, signal processing, GPS etc. This work proposes an area-efficient method for complex divider implementation on FPGA. The operands are represented in single precision floating point (IEEE754) format. A novel method called module reuse technique is used for reducing the device utilization on FPGA. The proposed design is analyzed using the simulation and implementation results on Xilinx Artix-7 and Virtex-5 FPGA families.