A 70.4 dB voltage gain, 2.3 dB NF, fully integrated multi-standard UHF receiver front-end in CMOS 130-nm. (June 2016) - Júnior, Carlos A.M. Costa; Filho, José B. Sales; Cunha, Gabriel C.L.; Belfort, Diomadson R.; Catunda, Sebastian Y.C.; de Lima, Robson N.; Bourguet, Vincent P.M.
Abstract: The design of a fully integrated multi-standard UHF receiver front-end to be embedded in environmental data collection satellites is proposed. The circuit operates under the requirements of both SBCDA and the ARGOS 3. For that, the specifications of a multi-standard receiver front-end are firstly derived and then the implementation of a 70.4 dB voltage gain, 2.3 dB NF, 48 mW energy consumption, single-ended input and differential quadrature output receiver front-end in 130-nm CMOS standard technology is presented. The design is validated through post-layout simulation.